Commit 08714a53 authored by Momin Charles's avatar Momin Charles

add last version of the code

parent 50f3202c
......@@ -28,6 +28,7 @@ wire [Nbits-1:0] ch_delta = ctrl_TK_addition ? delta : {Nbits{1'b0}};
wire [3:0] ch_W = ctrl_W_addition ? W : 4'b0;
// Key selection
(* KEEP = "TRUE", S = "TRUE", DONT_TOUCH = "TRUE" *)
wire [d*Nbits-1:0] sharing_zero;
cst_mask #(.d(d),.count(Nbits))
cst_zero(
......
......@@ -34,13 +34,10 @@ for(i=0; i<d; i=i+1) begin: igen
end
end
(* KEEP = "TRUE" *)
(* DONT_TOUCH = "TRUE" *)
(* S = "TRUE" *)
(* KEEP = "TRUE", S = "TRUE", DONT_TOUCH = "TRUE" *)
wire [d-1:0] not_ina = ~ina;
(* KEEP = "TRUE" *)
(* DONT_TOUCH = "TRUE" *)
(* S = "TRUE" *)
(* KEEP = "TRUE", S = "TRUE", DONT_TOUCH = "TRUE" *)
reg [d-1:0] inb_prev;
always @(posedge clk)
if(en) begin
......@@ -50,17 +47,11 @@ end else begin
end
for(i=0; i<d; i=i+1) begin: ParProdI
(* KEEP = "TRUE" *)
(* DONT_TOUCH = "TRUE" *)
(* S = "TRUE" *)
(* KEEP = "TRUE", S = "TRUE", DONT_TOUCH = "TRUE" *)
reg [d-2:0] u, v, w;
(* KEEP = "TRUE" *)
(* DONT_TOUCH = "TRUE" *)
(* S = "TRUE" *)
(* KEEP = "TRUE", S = "TRUE", DONT_TOUCH = "TRUE" *)
reg aibi;
(* KEEP = "TRUE" *)
(* DONT_TOUCH = "TRUE" *)
(* S = "TRUE" *)
(* KEEP = "TRUE", S = "TRUE", DONT_TOUCH = "TRUE" *)
wire aibi_comb = ina[i] & inb_prev[i];
always @(posedge clk)
if(en) begin
......@@ -72,17 +63,11 @@ for(i=0; i<d; i=i+1) begin: ParProdI
for(j=0; j<d; j=j+1) begin: ParProdJ
if (i != j) begin: NotEq
localparam j2 = j < i ? j : j-1;
(* KEEP = "TRUE" *)
(* DONT_TOUCH = "TRUE" *)
(* S = "TRUE" *)
(* KEEP = "TRUE", S = "TRUE", DONT_TOUCH = "TRUE" *)
wire u_j2_comb = not_ina[i] & rnd_mat_prev[i][j];
(* KEEP = "TRUE" *)
(* DONT_TOUCH = "TRUE" *)
(* S = "TRUE" *)
(* KEEP = "TRUE", S = "TRUE", DONT_TOUCH = "TRUE" *)
wire v_j2_comb = inb[j] ^ rnd_mat[i][j];
(* KEEP = "TRUE" *)
(* DONT_TOUCH = "TRUE" *)
(* S = "TRUE" *)
(* KEEP = "TRUE", S = "TRUE", DONT_TOUCH = "TRUE" *)
wire w_j2_comb = ina[i] & v[j2];
always @(posedge clk)
if(en) begin
......
......@@ -9,8 +9,8 @@ module MSKclyde_128
parameter PDSBOX = 2,
parameter PDLBOX = 1,
parameter Nbits=128,
parameter RND_RATE_DIVIDER = 1,
parameter SIZE_FEED = 32,
parameter RND_RATE_DIVIDER = 1,
parameter ALLOW_SPEED_ARCH=0
)
(
......@@ -26,8 +26,10 @@ module MSKclyde_128
pre_enable,
// PRNG ports //
feed1,
lock_feed1,
feed_data,
feed2,
lock_feed2,
ready_start_run
);
......@@ -55,8 +57,10 @@ output [Nbits-1:0] data_out;
output pre_data_out_valid;
input pre_enable;
input feed1;
input lock_feed1;
input [SIZE_FEED-1:0] feed_data;
input feed2;
input lock_feed2;
output ready_start_run;
// PRNG rnd1 SB //
......@@ -69,6 +73,7 @@ prng1(
.clk(clk),
.pre_rst(pre_syn_rst),
.pre_enable_run(pre_enable_run_prng1),
.lock_feed(lock_feed1),
.feed(feed1),
.feed_data(feed_data),
.rnd_valid_next_enable(rnd_valid_next_enable1),
......@@ -85,6 +90,7 @@ prng2(
.clk(clk),
.pre_rst(pre_syn_rst),
.pre_enable_run(pre_enable_run_prng2),
.lock_feed(lock_feed2),
.feed(feed2),
.feed_data(feed_data),
.rnd_valid_next_enable(rnd_valid_next_enable2),
......@@ -94,7 +100,9 @@ prng2(
// Clyde core //
wire [SIZE_SHARING-1:0] sharing_data_out;
wire pre_enable_core;
wire pre_pre_need_rnd1;
wire pre_need_rnd1;
wire pre_pre_need_rnd2;
wire pre_need_rnd2;
wire in_process_status;
wire dut_data_in_valid;
......@@ -120,18 +128,22 @@ clyde_core(
.pre_enable(pre_enable_core),
.rnd1_SB(rnd1),
.rnd2_SB(rnd2),
.pre_pre_need_rnd1_SB(pre_pre_need_rnd1),
.pre_need_rnd1_SB(pre_need_rnd1),
.pre_pre_need_rnd2_SB(pre_pre_need_rnd2),
.pre_need_rnd2_SB(pre_need_rnd2),
.in_process_status(in_process_status)
);
/////// Stalling mechanism ////////
stalling_unit #(.RND_RATE_DIVIDER(RND_RATE_DIVIDER))
stalling_unit #(.RND_RATE_DIVIDER(RND_RATE_DIVIDER))
stall_mec(
.clk(clk),
.pre_syn_rst(pre_syn_rst),
.pre_enable_glob(pre_enable),
.pre_pre_need_rnd1(pre_pre_need_rnd1),
.pre_need_rnd1(pre_need_rnd1),
.pre_pre_need_rnd2(pre_pre_need_rnd2),
.pre_need_rnd2(pre_need_rnd2),
.rnd_valid_next_enable1(rnd_valid_next_enable1),
.rnd_valid_next_enable2(rnd_valid_next_enable2),
......
......@@ -45,7 +45,9 @@ module MSKclyde_128_1R #(
pre_enable,
rnd1_SB,
rnd2_SB,
pre_pre_need_rnd1_SB,
pre_need_rnd1_SB,
pre_pre_need_rnd2_SB,
pre_need_rnd2_SB,
in_process_status
);
......@@ -116,8 +118,12 @@ input [SIZE_SB_RND-1:0] rnd1_SB /*verilator public*/;
(* fv_type="random", fv_count=0 *)
input [SIZE_SB_RND-1:0] rnd2_SB;
(* fv_type="control" *)
output pre_pre_need_rnd1_SB;
(* fv_type="control" *)
output pre_need_rnd1_SB;
(* fv_type="control" *)
output pre_pre_need_rnd2_SB;
(* fv_type="control" *)
output pre_need_rnd2_SB;
(* fv_type="control" *)
output in_process_status;
......@@ -131,7 +137,6 @@ reg syn_rst;
always@(posedge clk)
syn_rst <= pre_syn_rst;
////// GENERAL DATAPATH //////
// phi unit //////////
wire enable_phi;
......@@ -169,6 +174,7 @@ sh_b2c_sb(
// zero sharing //
localparam SIZE_CHUNK_COLS = Nbits/SB_DIVIDER;
(* KEEP = "TRUE", S = "TRUE", DONT_TOUCH = "TRUE" *)
wire [SIZE_SB_CHUNK-1:0] sharing_cols_chunk_zero;
cst_mask #(.d(d),.count(SIZE_CHUNK_COLS))
cst_cols_SB_0(
......@@ -177,6 +183,7 @@ cst_cols_SB_0(
);
// Feeding SB mux //
(* KEEP = "TRUE", S = "TRUE", DONT_TOUCH = "TRUE" *)
wire [SIZE_SB_CHUNK-1:0] sharing_cols_chunk_to_SB;
wire ctrl_enable_feed_SB;
MSKmux_par #(.d(d),.count(SIZE_CHUNK_COLS))
......@@ -226,6 +233,7 @@ wire [SIZE_SHARING-1:0] sharing_bundle_to_LB;
// zero sharing //
localparam SIZE_CHUNK_BUNDLE = Nbits/LB_DIVIDER;
(* KEEP = "TRUE", S = "TRUE", DONT_TOUCH = "TRUE" *)
wire [SIZE_LB_CHUNK-1:0] sharing_bundle_chunk_zero;
cst_mask #(.d(d),.count(SIZE_CHUNK_BUNDLE))
cst_bundle_LB_0(
......@@ -234,6 +242,7 @@ cst_bundle_LB_0(
);
// Feeding LB mux //
(* KEEP = "TRUE", S = "TRUE", DONT_TOUCH = "TRUE" *)
wire [SIZE_LB_CHUNK-1:0] sharing_bundle_chunk_to_LB;
wire ctrl_enable_feed_LB;
MSKmux_par #(.d(d),.count(SIZE_CHUNK_BUNDLE))
......@@ -322,6 +331,7 @@ state_reg(
);
// Output mux ////////////////////////////
(* KEEP = "TRUE", S = "TRUE", DONT_TOUCH = "TRUE" *)
wire [SIZE_SHARING-1:0] cst_sharing_zero;
cst_mask #(.d(d),.count(Nbits))
cst_zero_out(
......@@ -420,10 +430,12 @@ wire pre_rst_run = ~flag_in_process & ~next_flag_in_process;
wire end_r_computation = (mask_cnt == R_LAT-1);
// The round counter should be increased at the next clock cycle
wire pre_end_r_computation = (mask_cnt == R_LAT-2);
// Last round
wire last_round = (r_cnt == R_AMOUNT-1);
// Last clock cycle of the run
wire end_process = end_r_computation & (r_cnt == R_AMOUNT-1);
wire end_process = end_r_computation & last_round; //(r_cnt == R_AMOUNT-1);
// The next clock cycle is the last one of the run
wire pre_end_process = pre_end_r_computation & (r_cnt == R_AMOUNT-1);
wire pre_end_process = pre_end_r_computation & last_round; //(r_cnt == R_AMOUNT-1);
///// Control for the masking counter /////
wire pre_en_mask_cnt = pre_syn_rst | pre_enable;
......@@ -491,13 +503,31 @@ wire pre_need_rnd2_SB_DEC;
wire pre_need_rnd2_SB = inverse ? pre_need_rnd2_SB_DEC : pre_need_rnd2_SB_ENC;
// DEBUG //
wire pre_pre_need_rnd1_SB_ENC;
wire pre_pre_need_rnd2_SB_ENC;
wire pre_pre_need_rnd1_SB_DEC;
wire pre_pre_need_rnd2_SB_DEC;
assign pre_pre_need_rnd1_SB = inverse ? pre_pre_need_rnd1_SB_DEC : pre_pre_need_rnd1_SB_ENC;
assign pre_pre_need_rnd2_SB = inverse ? pre_pre_need_rnd2_SB_DEC : pre_pre_need_rnd2_SB_ENC;
generate
if(SB_DIVIDER==1) begin
assign pre_need_rnd1_SB_ENC = flag_in_process ? (end_r_computation & ~end_process) : 1'b1;
assign pre_need_rnd2_SB_ENC = flag_in_process ? (mask_cnt==0) & en_mask_cnt: 1'b0;
//
assign pre_pre_need_rnd1_SB_ENC = flag_in_process ? (pre_end_r_computation & ~last_round) : 1'b1;
assign pre_pre_need_rnd2_SB_ENC = flag_in_process ? (end_r_computation & ~last_round) : 1'b1;
end else begin
assign pre_need_rnd1_SB_ENC = flag_in_process ? (end_r_computation & ~end_process) | (mask_cnt < SB_DIVIDER-1) : 1'b1;
assign pre_need_rnd2_SB_ENC = flag_in_process ? (mask_cnt < SB_DIVIDER) & en_mask_cnt: 1'b0;
assign pre_need_rnd1_SB_ENC = flag_in_process ? ((end_r_computation & ~end_process) | (mask_cnt < SB_DIVIDER-1)) : 1'b1;
assign pre_need_rnd2_SB_ENC = flag_in_process ? (mask_cnt < SB_DIVIDER) : 1'b0;
//
assign pre_pre_need_rnd1_SB_ENC = flag_in_process ? ((pre_end_r_computation | end_r_computation) & ~last_round) | (mask_cnt < SB_DIVIDER-2) : 1'b1;
assign pre_pre_need_rnd2_SB_ENC = flag_in_process ? (mask_cnt < SB_DIVIDER-1) | (end_r_computation & ~last_round) : 1'b1;
end
endgenerate
......@@ -535,9 +565,15 @@ if(ALLOW_SPEED_ARCH) begin
if(LB_DIVIDER==1) begin
assign pre_need_rnd1_SB_DEC = pre_need_rnd1_SB_ENC;
assign pre_need_rnd2_SB_DEC = pre_need_rnd2_SB_ENC;
//
assign pre_pre_need_rnd1_SB_DEC = flag_in_process ? (mask_cnt < SB_DIVIDER-2) | ((pre_end_r_computation | end_r_computation) & ~last_round): 1'b1;
assign pre_pre_need_rnd2_SB_DEC = flag_in_process ? (mask_cnt<SB_DIVIDER-1) | (end_r_computation & ~last_round): 1'b1;
end else begin
assign pre_need_rnd1_SB_DEC = flag_in_process & (mask_cnt<SB_DIVIDER);
assign pre_need_rnd2_SB_DEC = flag_in_process & (mask_cnt-1<SB_DIVIDER) & (mask_cnt>0) & en_mask_cnt;
assign pre_need_rnd2_SB_DEC = flag_in_process & (mask_cnt-1<SB_DIVIDER) & (mask_cnt>0) ;
//
assign pre_pre_need_rnd1_SB_DEC = flag_in_process ? (mask_cnt<SB_DIVIDER-1) | (end_r_computation & ~last_round): 1'b1;
assign pre_pre_need_rnd2_SB_DEC = flag_in_process & (mask_cnt<SB_DIVIDER);
end
end else begin
......@@ -552,10 +588,16 @@ end else begin
if(LB_DIVIDER==1) begin
assign pre_need_rnd1_SB_DEC = flag_in_process & (mask_cnt<SB_DIVIDER);
assign pre_need_rnd2_SB_DEC = flag_in_process & (mask_cnt-1<SB_DIVIDER) & (mask_cnt>0) & en_mask_cnt;
assign pre_need_rnd2_SB_DEC = flag_in_process & (mask_cnt-1<SB_DIVIDER) & (mask_cnt>0);
//
assign pre_pre_need_rnd1_SB_DEC = flag_in_process ? (mask_cnt < SB_DIVIDER-1) | (end_r_computation & ~last_round): 1'b1;
assign pre_pre_need_rnd2_SB_DEC = flag_in_process & (mask_cnt < SB_DIVIDER) ;
end else begin
assign pre_need_rnd1_SB_DEC = flag_in_process & (mask_cnt-1<SB_DIVIDER);
assign pre_need_rnd2_SB_DEC = flag_in_process & (mask_cnt-2<SB_DIVIDER) & (mask_cnt>1) & en_mask_cnt;
assign pre_need_rnd2_SB_DEC = flag_in_process & (mask_cnt-2<SB_DIVIDER) & (mask_cnt>1) ;
//
assign pre_pre_need_rnd1_SB_DEC = flag_in_process & (mask_cnt<SB_DIVIDER);
assign pre_pre_need_rnd2_SB_DEC = flag_in_process & (mask_cnt-1<SB_DIVIDER) & (mask_cnt>0);
end
end
......
......@@ -45,6 +45,7 @@ prng_unit #(.SIZE_RND(SIZE_RND_RFSH),.SIZE_GEN(SIZE_RND_GEN),.SIZE_FEED(SIZE_FEE
prng_core(
.pre_enable_run(pre_enable_run_prng),
.pre_rst(pre_rst),
.lock_feed(~n_lock_for_seed),
.clk(clk),
.feed(feed_prng_seed & data_in_valid),
.feed_data(data_in),
......@@ -52,7 +53,7 @@ prng_core(
.rnd_out(rnd)
);
assign pre_enable_run_prng = (~rnd_ready & n_lock_for_seed) | pre_pre_refresh | pre_rst;
assign pre_enable_run_prng = ~rnd_ready| pre_pre_refresh | pre_rst;
// Key holder unit
MSKkey_holder #(.d(d),.Nbits(Nbits),.FEED_SIZE(SIZE_FEED))
......
......@@ -21,9 +21,7 @@ input enable;
// spook K4D2F2 --> depth 2 and 1 on one input of the 2nd layer and to reduce delay on refresh on the critical-path
wire [d-1:0] rfrs1, rfrs2, rfrs3, rfrs4, temp_out2, temp_out3;
// FF on the other AND input and synchronization/pipelining
(* KEEP = "TRUE" *)
(* DONT_TOUCH = "TRUE" *)
(* S = "TRUE" *)
(* KEEP = "TRUE", S = "TRUE", DONT_TOUCH = "TRUE" *)
wire [d-1:0] x0F, x1F, x2F, x1FF, x2FF, q1F, l1F, l1FF, l2F, q7F, l0F, l0FF, l0FFF, t2F, temp_out2F, temp_out3F;
wire [d-1:0] l0, l1, l2, l3, l4, q1, q2, q5, q6, q7, t0, t1, t2, t3, l2xt2;
......
......@@ -11,6 +11,7 @@ module prng_unit
)
(
input pre_enable_run,
input lock_feed,
input pre_rst,
input clk,
input feed,
......@@ -18,18 +19,19 @@ module prng_unit
input [SIZE_FEED-1:0] feed_data,
// The rnd is valid 1 cycle the next time the core is enabled.
output rnd_valid_next_enable,
output pre_rnd_valid_next_enable,
output [SIZE_RND-1:0] rnd_out
);
// Global enable signal //
reg glob_enable;
always@(posedge clk)
glob_enable <= pre_rst | feed | pre_enable_run;
glob_enable <= pre_rst | feed | (~lock_feed & pre_enable_run);
// Feeding flag //
reg ctrl_feed;
always@(posedge clk)
ctrl_feed <= feed;
ctrl_feed <= feed | lock_feed;
reg [SIZE_FEED-1:0] feed_data_barrier;
always@(posedge clk)
......@@ -86,52 +88,94 @@ endgenerate
// Randomness handling
localparam RND_LAT = SIZE_RND / SIZE_GEN;
parameter CNT_SIZE = ((RND_LAT % 2) == 0) ? $clog2(RND_LAT) : $clog2(RND_LAT) + 1;
localparam BUF_SIZE = SIZE_RND-SIZE_GEN;
parameter CNT_SIZE = $clog2(RND_LAT) + 1;
// Buffer reg (used to avoid glitches)
(* KEEP = "TRUE", S = "TRUE", DONT_TOUCH = "TRUE" *)
wire [SIZE_RND-1:0] next_rnd_buffer;
dff #(.SIZE(SIZE_RND),.ASYN(0))
rnd_buffer_reg(
.clk(clk),
.rst(1'b0),
.d(next_rnd_buffer),
.en(glob_enable),
.q(rnd_out)
);
generate
if(RND_LAT == 1) begin
assign rnd_valid_next_enable = ~rst;
assign rnd_out = Q;
end else begin
// Randomness generated in multiple cycles
wire [BUF_SIZE-1:0] rnd_buffer;
wire [BUF_SIZE-1:0] next_rnd_buffer;
wire rst_rnd_cnt;
dff #(.SIZE(BUF_SIZE),.ASYN(0))
rnd_buffer_reg(
// rnd_validity
wire rnd_validity;
wire next_rnd_validity = glob_enable & ~lock_feed;
wire rst_rnd_validity = feed | lock_feed;
dff #(.SIZE(1),.ASYN(0))
dff_rnd_valid(
.clk(clk),
.rst(1'b0),
.d(next_rnd_buffer),
.rst(rst_rnd_validity),
.d(next_rnd_validity),
.en(glob_enable),
.q(rnd_buffer)
.q(rnd_validity)
);
if(BUF_SIZE==SIZE_GEN) begin
assign next_rnd_buffer = Q;
end else begin
assign next_rnd_buffer = {Q,rnd_buffer[SIZE_GEN +: BUF_SIZE-SIZE_GEN]};
end
assign rnd_valid_next_enable = rnd_validity;
assign pre_rnd_valid_next_enable = next_rnd_validity | rnd_validity;
assign next_rnd_buffer = Q;
end else begin
// Todo add pre_rnd_valid_next_enable.
// Randomness generated in multiple cycles
wire rst_rnd_cnt;
wire init_generation_done;
wire pre_pre_buffer_full;
wire pre_buffer_full;
wire buffer_full;
wire [CNT_SIZE-1:0] rnd_cnt;
wire [CNT_SIZE-1:0] next_rnd_cnt = rnd_cnt + 1'b1;
wire pre_process_rnd = rnd_valid_next_enable & pre_enable_run;
wire buffer_full = rnd_cnt == (RND_LAT-1);
assign rst_rnd_cnt = (buffer_full & pre_process_rnd) | rst | ctrl_feed;
if(RND_LAT==2) begin
assign pre_pre_buffer_full = init_generation_done ? rst_rnd_cnt : (rnd_cnt == 0);
end else begin
assign pre_pre_buffer_full = (init_generation_done ? (rnd_cnt == RND_LAT-3) : (rnd_cnt == RND_LAT-2)) & ~rst_rnd_cnt;
end
assign pre_buffer_full = (init_generation_done ? (rnd_cnt == RND_LAT-2) : (rnd_cnt == RND_LAT-1)) & ~rst_rnd_cnt;
assign buffer_full = init_generation_done ? (rnd_cnt == (RND_LAT-1)) : (rnd_cnt == RND_LAT);
assign rst_rnd_cnt = (buffer_full & glob_enable) | rst | ctrl_feed;
dff #(.SIZE(CNT_SIZE),.ASYN(0))
rnd_cnt_reg(
.clk(clk),
.rst(rst_rnd_cnt),
.d(next_rnd_cnt),
.en(glob_enable),
.en(glob_enable & ~buffer_full),
.q(rnd_cnt)
);
assign rnd_valid_next_enable = (((rnd_cnt == (RND_LAT-2)) & glob_enable & ~ctrl_feed) | (buffer_full & ~glob_enable)) & ~rst;
assign rnd_out = {Q,rnd_buffer};
wire rst_init_flag = rst | ctrl_feed;
dff #(.SIZE(1),.ASYN(0))
dff_init_gen(
.clk(clk),
.rst(rst_init_flag),
.d(buffer_full | init_generation_done),
.en(glob_enable),
.q(init_generation_done)
);
assign rnd_valid_next_enable = (( pre_buffer_full & glob_enable & ~ctrl_feed & ~rst_rnd_cnt) | (buffer_full & ~glob_enable)) & ~rst;
if(RND_LAT==2) begin
assign pre_rnd_valid_next_enable = ((pre_pre_buffer_full & glob_enable & ~ctrl_feed) | (pre_buffer_full & ~glob_enable)) & ~rst;
end else begin
assign pre_rnd_valid_next_enable = ((pre_pre_buffer_full & glob_enable & ~ctrl_feed & ~rst_rnd_cnt) | (pre_buffer_full & ~glob_enable)) & ~rst;
end
assign next_rnd_buffer = {Q,rnd_out[SIZE_GEN +: SIZE_RND-SIZE_GEN]};
end
endgenerate
......
......@@ -3,14 +3,17 @@
randomness generation.
*/
module stalling_unit
#(
parameter RND_RATE_DIVIDER = 2
#
(
parameter RND_RATE_DIVIDER = 1
)
(
input clk,
input pre_syn_rst,
input pre_enable_glob,
input pre_pre_need_rnd1,
input pre_need_rnd1,
input pre_pre_need_rnd2,
input pre_need_rnd2,
input rnd_valid_next_enable1,
input rnd_valid_next_enable2,
......@@ -32,72 +35,83 @@ reg syn_rst;
always@(posedge clk)
syn_rst <= pre_syn_rst;
// prng ready to start
wire init_config = ~core_in_process;
wire prng1_rdy = rnd_valid_next_enable1;
wire prng2_rdy = rnd_valid_next_enable2;
wire prngs_rdy = prng1_rdy & prng2_rdy;
// The core is ready to start a new run
assign ready_start_run = ~core_in_process;
// A new run starts
wire start_run_acknowledgement = ready_start_run & pre_data_in_valid;
wire valid_start_run;
assign ready_start_run = prngs_rdy & init_config & ~valid_start_run;
wire start_run_acknowledged;
// Valid start run
wire valid_pre_start_run = pre_data_in_valid & ready_start_run;
dff #(.SIZE(1),.ASYN(0))
prev_start_acknoledged_reg(
dff_started(
.clk(clk),
.rst(syn_rst),
.d(start_run_acknowledgement),
.d(valid_pre_start_run),
.en(enable_stalling_reg),
.q(start_run_acknowledged)
.q(valid_start_run)
);
/////// Status of randomness 1 ///////
// Stalling register prng1 //
wire next_stall_from_prng1;
wire stall_from_prng1;
// Stall registers
wire stall_from_prng1, stall_from_prng2;
wire next_flag_stall1, next_flag_stall2;
wire flag_stall1, flag_stall2;
wire rst_f1, rst_f2;
dff #(.SIZE(1),.ASYN(0))
stall_reg1(
dff_stall1(
.clk(clk),
.rst(syn_rst),
.d(next_stall_from_prng1),
.rst(rst_f1),
.d(next_flag_stall1),
.en(enable_stalling_reg),
.q(stall_from_prng1)
.q(flag_stall1)
);
// Stalling register prng2 //
wire next_stall_from_prng2;
wire stall_from_prng2;
dff #(.SIZE(1),.ASYN(0))
stall_reg2(
dff_stall2(
.clk(clk),
.rst(syn_rst),
.d(next_stall_from_prng2),
.rst(rst_f2),
.d(next_flag_stall2),
.en(enable_stalling_reg),
.q(stall_from_prng2)
.q(flag_stall2)
);
wire init_pre_need_rnd = pre_need_rnd1 & start_run_acknowledged;
wire init_stall_req = init_pre_need_rnd & ~rnd_valid_next_enable1;
assign stall_from_prng1 = pre_need_rnd1 & ~rnd_valid_next_enable1;
assign stall_from_prng2 = pre_need_rnd2 & ~rnd_valid_next_enable2;
assign next_flag_stall1 = stall_from_prng1 | flag_stall1;
assign next_flag_stall2 = stall_from_prng2 | flag_stall2;
wire in_proc_pre_need_rnd1 = core_in_process & (pre_need_rnd1 | stall_from_prng1);
wire in_proc_stall_req1 = in_proc_pre_need_rnd1 & ~rnd_valid_next_enable1;
assign rst_f1 = syn_rst | flag_stall1 & rnd_valid_next_enable1;
assign rst_f2 = syn_rst | flag_stall2 & rnd_valid_next_enable2;
wire in_proc_pre_need_rnd2 = core_in_process & (pre_need_rnd2 | stall_from_prng2);
wire in_proc_stall_req2 = in_proc_pre_need_rnd2 & ~rnd_valid_next_enable2;
// Core enable and glob ready signals //
wire stalled_core = flag_stall1 | flag_stall2;
assign next_stall_from_prng1 = init_stall_req | in_proc_stall_req1;
assign next_stall_from_prng2 = in_proc_stall_req2;
wire stall_req = stall_from_prng1 | stall_from_prng2;
wire pre_need_rnd = pre_need_rnd1 | pre_need_rnd2;
wire pre_pre_need_rnd = pre_pre_need_rnd1 | pre_pre_need_rnd2;
// The pre enable signal of the PRNG
assign pre_enable_run_prng1 = init_pre_need_rnd | in_proc_pre_need_rnd1;
assign pre_enable_run_prng2 = in_proc_pre_need_rnd2;
generate
if (RND_RATE_DIVIDER==1) begin
assign pre_enable_run_prng1 = init_config ? (prng1_rdy ? valid_pre_start_run | (valid_start_run & rnd_valid_next_enable1) : (valid_start_run ? pre_pre_need_rnd1 : 1'b1)) : (stall_from_prng1 | flag_stall1) & ~rnd_valid_next_enable1 | pre_pre_need_rnd1;
// Core enable and glob ready signals ///
wire init_mask_pre_enable_core = start_run_acknowledgement | (start_run_acknowledged & ~init_stall_req);
wire in_proc_mask_pre_en_prng1 = (rnd_valid_next_enable1 | ~(pre_need_rnd1 | stall_from_prng1));
wire in_proc_mask_pre_en_prng2 = (rnd_valid_next_enable2 | ~(pre_need_rnd2 | stall_from_prng2));
wire in_proc_mask_pre_enable_core = core_in_process & in_proc_mask_pre_en_prng1 & in_proc_mask_pre_en_prng2;
assign pre_enable_run_prng2 = init_config ? (prng2_rdy ? valid_pre_start_run | (valid_start_run & rnd_valid_next_enable2) : (valid_start_run ? pre_pre_need_rnd2 : 1'b1)) : (stall_from_prng2 | flag_stall2) & ~rnd_valid_next_enable2 | pre_pre_need_rnd2;
end else begin
assign pre_enable_run_prng1 = init_config ? (prng1_rdy ? valid_pre_start_run | (valid_start_run & rnd_valid_next_enable1) : (valid_start_run ? pre_pre_need_rnd1 : 1'b1)) : (stall_from_prng1 | flag_stall1) & ~rnd_valid_next_enable1 | pre_pre_need_rnd1 | pre_need_rnd1;
wire mask_pre_enable_core = init_mask_pre_enable_core | in_proc_mask_pre_enable_core;
assign pre_enable_core = pre_enable_glob & mask_pre_enable_core;
assign pre_enable_run_prng2 = init_config ? (prng2_rdy ? valid_pre_start_run | (valid_start_run & rnd_valid_next_enable2) : (valid_start_run ? pre_pre_need_rnd2 : 1'b1)) : (stall_from_prng2 | flag_stall2) & ~rnd_valid_next_enable2 | pre_pre_need_rnd1 | pre_pre_need_rnd2 | pre_need_rnd2;
end
endgenerate
assign data_in_valid = start_run_acknowledged;
assign pre_enable_core = pre_enable_glob & (init_config ? (valid_pre_start_run) | (valid_start_run & (pre_need_rnd ? ~stall_req : 1'b1)) : (stalled_core ? (flag_stall1 & rst_f1) | (flag_stall2 & rst_f2) : ((pre_pre_need_rnd | pre_need_rnd) ? ~stall_req : 1'b1)));
assign data_in_valid = valid_start_run;
endmodule
......@@ -66,6 +66,8 @@ module controller
to_dp_clyde_pre_enable,
to_dp_clyde_en_feeding_prng1,
to_dp_clyde_en_feeding_prng2,
to_dp_clyde_lock_feed1,
to_dp_clyde_lock_feed2,
from_dp_clyde_ready_start,
// Encoder ///////////////
......@@ -153,6 +155,8 @@ input from_dp_clyde_pre_data_out_valid;
output to_dp_clyde_pre_enable;
output to_dp_clyde_en_feeding_prng1;
output to_dp_clyde_en_feeding_prng2;
output to_dp_clyde_lock_feed1;
output to_dp_clyde_lock_feed2;
input from_dp_clyde_ready_start;
output [3:0] to_encod_dtype;
......@@ -237,6 +241,8 @@ spook_core(
.to_dp_clyde_pre_enable(to_dp_clyde_pre_enable),
.to_dp_clyde_en_feeding_prng1(to_dp_clyde_en_feeding_prng1),
.to_dp_clyde_en_feeding_prng2(to_dp_clyde_en_feeding_prng2),
.to_dp_clyde_lock_feed1(to_dp_clyde_lock_feed1),
.to_dp_clyde_lock_feed2(to_dp_clyde_lock_feed2),
.from_dp_clyde_ready_start(from_dp_clyde_ready_start),
// Other controllers ///////////
......
......@@ -52,6 +52,8 @@ module datapath
clyde_pre_enable,
clyde_en_feeding_prng1,
clyde_en_feeding_prng2,
clyde_lock_feed1,
clyde_lock_feed2,
clyde_ready_start,
// Encoder //////////////
to_enc_bundle_blck_out,
......@@ -108,6 +110,8 @@ output clyde_pre_data_out_valid;
input clyde_pre_enable;
input clyde_en_feeding_prng1;
input clyde_en_feeding_prng2;
input clyde_lock_feed1;
input clyde_lock_feed2;
output clyde_ready_start;
// Encoder //////////////
output [n-1:0] to_enc_bundle_blck_out;
......@@ -194,8 +198,10 @@ clyde_core(
.data_out(clyde_data_out),
.pre_data_out_valid(clyde_pre_data_out_valid),
.pre_enable(clyde_pre_enable),
.lock_feed1(clyde_lock_feed1),
.feed1(clyde_en_feeding_prng1),
.feed_data(from_decod_data_in),
.lock_feed2(clyde_lock_feed2),
.feed2(clyde_en_feeding_prng2),
.ready_start_run(clyde_ready_start)
);
......
......@@ -104,6 +104,8 @@ wire from_dp_clyde_pre_data_out_valid;
wire to_dp_clyde_pre_enable;
wire to_dp_clyde_en_feeding_prng1;
wire to_dp_clyde_en_feeding_prng2;
wire to_dp_clyde_lock_feed1;
wire to_dp_clyde_lock_feed2;
wire from_dp_clyde_ready_start;
// Controller <-> Encoder
......@@ -221,6 +223,8 @@ cntrl_core (
.to_dp_clyde_pre_enable(to_dp_clyde_pre_enable),
.to_dp_clyde_en_feeding_prng1(to_dp_clyde_en_feeding_prng1),
.to_dp_clyde_en_feeding_prng2(to_dp_clyde_en_feeding_prng2),
.to_dp_clyde_lock_feed1(to_dp_clyde_lock_feed1),
.to_dp_clyde_lock_feed2(to_dp_clyde_lock_feed2),
.from_dp_clyde_ready_start(from_dp_clyde_ready_start),
// Controller <-> Encoder
......@@ -293,6 +297,8 @@ datapath_core (
.clyde_pre_enable(to_dp_clyde_pre_enable),
.clyde_en_feeding_prng1(to_dp_clyde_en_feeding_prng1),
.clyde_en_feeding_prng2(to_dp_clyde_en_feeding_prng2),
.clyde_lock_feed1(to_dp_clyde_lock_feed1),
.clyde_lock_feed2(to_dp_clyde_lock_feed2),
.clyde_ready_start(from_dp_clyde_ready_start),
// Encoder //////////////
.to_enc_bundle_blck_out(to_enc_bundle_blck_out),
......